Perl, Verilog, Python

Nvme, DDR, Pcie, Verilog, System Verilog, Uvm, code coverage analysis, Axi, functional coverage coding, RTL debugging, scoreboard assertions, AHB

synopsys primetime , Static Timing Analysis, STA methodologies, digital design principles, Constraints Manager, semiconductor fabrication processes, STA tools, Physical Design, Cadence Tempus

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, FPGA and emulation platforms, Dft, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification

random testing , Oops, Pcie, Verilog, Debugging, System Verilog, FPGA verification, coverage assertions, Ethernet based protocols, Otn, VCS simulation flow, Uvm, VMM, AXI memory controllers, adversarial testing

DDR, Perl, Verilog, Python, Tcl, spyglass, Axi, MIPI, AMBA, EDA Tools, Synopsys Design Compiler, LPDDR, AHB