Verilog, Usb, Tcl, Ethernet, Git, Ecos, C, Perforce, Python, Pcie, DDR, Xilinx Vivado, systemverilog, Cadence, static RTL checks, Synthesis, Axi, FPGA design tools, Mentor simulation suites, Intel Quartus, AMBA bus protocols, low power design techniques, Rtl Design, Lattice Diamond, STA timing closure, SoC architectures

debugging and problem-solving skills, digital logic design using FPGAs, Timing Analysis, Timing Closure, Verilog RTL design, FPGA Design Flow