Vc, Perl, Verilog, Python, System Verilog, Tcl, LINT, cdc, Vlsi, front-end design verification techniques, formal verification tools, LEC, spyglass, FV, Synthesis, RDC, Design Compilers, EDA Tools, ASIC Design

Perl, Python, Tcl, Clock domain partitioning, Power integrity and power-aware physical implementation, Block and subsystem-level physical design flows, primetime, Fusion Compiler, Clock gating, Congestion analysis and resolution, Clock tree architecture, Tempus, Cadence Innovus, Skew management, Certus, Synopsys ICC2, Timing closure and constraint management

Fpga, Perl, Python, Emulation, RTL, Uvm, systemverilog

Rtos, Embedded Linux, Uart, Spi, Git, Ipc Mechanisms, I2c, C Programming, Python, BACnet, Modbus, Linux process management

clocking , power integrity , LV EM IR Analysis, ESD Analysis, Physical Design Integration, RTL2GDS Implementation, Signal Integrity, PPA Power DRC Signoff, LVS clean-up, DRC, PNR Floor Plan, Power Mesh, Timing Signoff

Verilog, multi-clock designs, Synthesis, formal verification, ECO fixes, SoC clocking reset architecture, Logic design RTL coding, SoC design and integration, Timing Concepts, asynchronous interfaces, System-Verilog

arm architecture , Verilog, Device Drivers, C, Systemc, AHB, FPGA prototyping, systemverilog, Zephyr RTOS, RISC-V, register-level firmware, APB, Axi, hardware software interfaces, hardware emulation environments, Veloce, BUS Protocols, RTL, HALs, Embedded Linux kernel driver development, TLM 2.0, register maps, DMA, interrupt handling, Palladium