Wireshark, Zigbee, Wlan, Thread, Python, Iperf, Ellisys sniffers, Bluetooth BR, LE Audio

Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

Python, Analog Mixed-Signal circuits, EDA Tools, Cadence, systemverilog, Verilog-A

Python, Jasper VC Formal, formal verification, Property-based FV, Formal Tools, SVA, Questa Formal

Asic verification, digital design verification, Uvm, test bench architecture, systemverilog, GIT version control, C Language

Perl, Verilog, Python, System Verilog, UVM Methodology, Arm CoreSight IP, AMBA protocols, Testbench development

test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors