static timing analysis, Perl, Python, Tcl, multi-clock domain designs, constraint development, STA tools, clock gating, Cadence synthesis tools, Timing Analysis, CPF-based power intent, multi-voltage domains, UPF, ECO flows, timing convergence, RTL-to-gate synthesis, Timing Closure, low-power design techniques, constraint validation

simics , Software Architecture, Computer Architecture, Python, System C, gem5, qemu, RISC-V architecture, Virtualizer

Dynamodb, Vue.JS, Lambda, RDBMS, Cloudwatch, Docker, Terraform, ECS, Flask, Dynatrace, Splunk, FastAPI, Python, AWS, Api Gateway, Harness, GitHub Actions, Fargate, Next.js

Cadence - Virtuoso, Tcl, Python, Perl, Spice Simulator, Synopsys, Uvm, SV, Mentor tools, Verilog-A, Verilog-D, Cadence, Verilog Hdl, Verilog-AMS, AMS simulation environment

Kubernetes, Sql, Angular, Java, Python, Nosql, Docker, Reactjs, Restful Apis, micro-services architectures

Etl Testing, Dwh Testing, Dataware House Testing, Bigdata Testing

Nosql, Java, Restful Apis, Kubernetes, Python, Sql, Agentic AI, AI productivity tools, Go

Jenkins, Pytest, Python, Gdb, Azure DevOps, PDB, GTest, GitHub Actions, VSCode debugger, GitLab CI, PyCharm debugger, CLion