Verilog, Tcl, Python, Perl, Logic equivalence checking, EDA Tools, RTL synthesis

python, perl, Power Bi, Software Developement, Excel, Cadence, cliosoft

Tcl Scripting, Python, Synopsys DFT flow, Tool installation configuration, Dft, PrimePower, Virtuoso SI2 scripting, virtuoso, LEC, Voltus RedHawk, Power and signoff flow automation

hardware engineering , C, Makefile, Shell Scripting, UNIX, Perl, Python, Tcl, DPI C, data-management software, GLS Timing Simulations, UPF Verification, Design Verification, Object-Oriented software development, CAD Tools, systemverilog, Low Power solutions, EDA software flows, RTL Verilog, EDA Tools, Digital Verification methodologies, PSS Portable Stimulus, Front-end Digital Design

Python, Tcl Scripting, Dft, LEC, Virtuoso SI2 scripting, Power and signoff flow automation, Tool installation configuration, Synopsys DFT flow, PrimePower, Voltus RedHawk, virtuoso

Tcl Scripting, Power Grid design, floorplanning, Upstream Downstream flow correlation, Cadence Innovus tool, SI EM IR complex DRC rules, Timing Closure, Routability, Power intent, High speed and low power implementation techniques, Clock synthesis, Multiple power domains

Tcl Scripting, Routability, SI EM IR complex DRC rules, Timing Closure, Multiple power domains, Clock synthesis, Power intent, Power Grid design, floorplanning, High speed and low power implementation techniques, Upstream Downstream flow correlation, Cadence Innovus tool