power integrity , Routing, Perl, Python, Tcl, Chip finishing, Metal fill, Clock Trees, Tapeout checks, Physical Verification, Sealring, Signal Integrity, RTL2GDS flow, Floorplans, Power Distribution Network, Physical Design, Timing Closure, Placement, Physical Sign off, Equivalence Check, Synthesis Constraints

Mentor, Uvm, firmware interaction, Synopsys, AMs, systemverilog, Cadence, Siemens, Calibration and link training flows, Register models, industry VIPs, Avery, SERDES

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

IP SoC verification, ASIC-SoC design verification, systemverilog

synopsys tools , Tcl, Python, Linux, Sram, Memory compilers, primetime, Cadence Virtuoso, Design Compiler, Spectre, Hspice, Rom

IP SoC verification, ASIC-SoC design verification, systemverilog