Python, Perl, Logic Design, Profiling Tools, Uvm, Post Silicon Testing, SV, Constrained random testing, Architecture Verification, DFT Engineering, Coverage metrics

Unix, Svn, Shell, Report Automation, Linux, Verilog, Tcl, Python, Perl, Git, Cadence Modus, MBIST, Scan compression, Scan architecture, log parsing, TestMAX, systemverilog, ATPG, DFT fundamentals, TetraMax, Synopsys DFT Compiler, LBIST, flow orchestration

memory test , boundary scan , Digital Logic Design, static timing analysis, Hdl, Jtag, DFX verification, HTOL, test clocking, security mechanisms, compression techniques, IDDQ, IEEE1149.1, Gates verification, Eco, ATPG, BIST architecture, silicon bring-up, Scan ATPG, ASIC Logic Design Flow, reliability tests