hierarchical layout techniques, 3nm technology, custom layout design, Mentor Graphics Calibre, Totem tools, Cadence Innovus, device matching, Cadence XL, designing custom analog blocks, full-chip integration, IR drop analysis, low-parasitic layout practices

Scripting Languages, Sta, Synthesis, Flow development, PNR, Digital Implementation flow, debugging skills, ML based Solutions

Shell, Python, Tcl, Cadence SKILL programming, Debugging and problem-solving, Layout verification flows DRC LVS, Analog and mixed-signal layout methodologies, Techfile customization, Cadence Virtuoso layout environment, PDK development concepts

synopsys primetime , Perl, Python, Tweaker, Power-Aware Verification UPF, Cadence CCD, Sign-off STA Synopsys PrimeTime PT PT-PX, Cadence Conformal LEC, PrimeClosure, Cadence Tempus, Synopsys Formality, Formal Verification LEC, Constraints Validation Synopsys TCM GCA Ausdia TimeVision SpyGlass, Timing Closure ECO Cadence Tempus

production readiness , power analysis, Design Reviews, Silicon Bring-up, PnR Implementation, Verification, Physical Design, Placement, Floor Planning, ASIC Design, Low Power Verification, Rtl Design

Test automation, Integration And System Testing, Qualification of Vendors, Six Sigma Methodology, Exposure to Regulatory Standards Manufacturing process and procedure for, Systems Component level Verification Validation, Understanding of hardware methodologies and test best practices, IQ OQ and PQ for equipments Instruments, Design verification and validation of medical devices, Technical testing reliability experience in Plastic Connectors Products electro-mechanical, RF welding Solvent bonding process, Statistical tools like Minitab

Custom layout design, High-speed IPs, Floorplan constraints, High-speed Analog Serdes, Data converters, LVS, Scripting and automation, Analog Macros, IP integration, Pll, Physical verifications, Analog layout techniques, power management, DRC, Ageing and Reliability Compliance, Full Spectrum Verifications, Electrical check