Tcl, Shell scripting, Python, Vcs, Perl, Uvm, NC-Sim, systemverilog

Data Privacy, Kaizen, Interpersonal Skills, Rf, Automotive Electronics, Electronics, Simulation, Signal Processing

Vcs, Soc Architecture, Pcie, System integration, Fc, LINT, Dc, cdc, Memory, IP integration, Synthesis, RDC, SOC design execution, Low-power implementation, VCLP, Physical design feedback, coverage gap analysis, multi-die methodology, debug failures, Formality, LEC, SOC Connectivity, Axi, spyglass, Equivalence Check, System bus and IO protocol understanding

rtl development , Uart, Spi, Pcie, Verilog, I2c, System Verilog, Cadence Tools, scripting Python, gate-level simulations, Synthesis, Design Verification, DMA engines, micro-architecture development, front-end design, Timing Closure, UVM-based design verification, processor IP ARM

SPICE simulators, PVT corner analysis, mixed-signal verification methodologies, SPICE-level validation, SoC Verification, mixed-signal co-simulation tools, gate-level simulations, SystemVerilog UVM, Synopsys CustomSim, AMS co-simulation platforms, analog-digital interaction verification, digital-first verification tools, real-number modeling RNM, analog-digital interaction testing, Cadence Virtuoso AMS Designer, Co-simulation methodologies

Security Solutions, AI-ready Ethernet Fabrics, Cloud Networking Observability, Campus Wi-Fi, GSP Model, Network Security Automation, networking infrastructure, Data Center Switching