simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog

DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet

Fpga, Perl, Python, object-oriented programming, RTL, test plan development, Uvm, emulation platforms, systemverilog, automation scripts

Verilog, Scripting Languages, Verification Tools, Simulators, formal verification, VHDL, Uvm

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB

Fpga, Perl, Python, object-oriented programming, RTL, emulation platforms, test plan development, Uvm, automation scripts, systemverilog

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, Specman E, hierarchical memory subsystems, Debug, IP subsystem SoCs, congestion control, regression systems, systemverilog, vector processing units, full verification life cycle, revision control systems, AI ML Accelerators, constrained-random verification environments, packet processing, Verification

Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB

Perl, Verilog, Python, Tcl, Synopsys VCS, Mentor Questa, VHDL, Cadence Xcelium, Uvm, systemverilog, SVA