C, Shell, Perl, Verilog, Debugging, System Verilog, Python, Tcl, Metric Driven Verification, Uvm, formal verification methodologies, assertions

Ovm, Verilog, Python, Functional Verification, Asic verification, formal verification, systemverilog, Uvm

Tcl, Verilog, Python, Perl, Uvm, SVA, VHDL, systemverilog

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC

C, Fpga, Soc Architecture, Verilog, Scripting Languages, systemverilog, digital logic design principles, logic synthesis techniques, RTL design concepts, ASIC design methodologies, emulation platforms, low-power design techniques, assertion-based formal verification

Unix, C, Pcie, Linux, Verilog, Ethernet, Python, Systemc, SERDES, Uvm, systemverilog, USB 3.0

Linux O.S., System Verilog, Python, Perl, Arm Assembly, Networking Protocols, Uvm, Object-Oriented Design, EDA Verification tools