rtl development , Vcs, Gdb, Shell, Perl, Verilog, Python, ASIC design flow, floor-planning, scripting knowledge, Simulation Tools, Timing Analysis, debug tools, Logic Synthesis, Eco, design and verification tools, micro-architecture, Debussy, bring-up lab debug

rtl development , Verilog, Vcs, Simulation Tools, ASIC design flow, Timing Analysis, design and verification tools, debug tools, micro-architecture