Tcp, Pcie, Ethernet, System Verilog, RDMA, Palladium, Test benches, Zebu, Veloce, ASIC verification using UVM, HAPS, Data path verification, formal verification

Tcp, Pcie, Ethernet, System Verilog, RDMA, Data path verification performance tests, Building test benches, Palladium, Zebu, Veloce, ASIC verification using UVM, HAPS, formal verification

System Verilog, Tcp, Ethernet, Pcie, formal verification, Data path verification performance tests, Building test benches, RDMA, Zebu, HAPS, ASIC verification using UVM, Palladium, Veloce

display technologies , Python Programming, Bit Depth Color, Bitstream Verification, MIPI DSI-2, Linux DRM KMS drivers, Introspect SV series systems, Uvm, High-speed oscilloscopes, systemverilog, Scaling Processing, Multimeters, PVT Testing, Frame Buffer, HWC, Android SurfaceFlinger, Logic analyzers, Pixel Formats, Low-Level Software

Cache, Soc Architecture, Verilog, power analysis, Synthesis, memory compression, FPGA design verification, digital logic design principles, systemverilog, logic synthesis techniques, RTL design concepts, FPGA and emulation platforms, Dft, fabric coherence, DRAM, low-power design techniques, assertion-based formal verification