power optimization , Static Timing Analysis, power analysis, low power design techniques, SoC integration, Design-for-Test, constraints development for Physical Design implementation, Design-for-Debug, SoC Debug architectures

Vcs, Tcl, Verilog, System Verilog, Python, Perl, Sec, Questa, spyglass, LINT, Xcelium, cdc, Jasper-FPV, Questa CDC, RDC