power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

Rtos, Uart, Zephyr, Spi, Embedded Linux, Pcie, I2c, Python, peripheral drivers, lab instrumentation, protocol analyzers, platform firmware development, Oscilloscopes, embedded firmware systems, BootROM, secure boot development

Perl, Verilog, Python

Usb, C, Nvme, Pcie, Verilog, Python, eMMC, Sd, NAND

synopsys primetime , Python Scripting, Design Compiler, SDC constraint authoring and management, Physical-aware synthesis flows, Fusion Compiler, Formality, Physical-Aware Synthesis, STA PrimeTime

Perl, Vcs, Python, Tcl, ASIC Verification using SystemVerilog, NC, Uvm