random testing , Oops, Fpga, Pcie, Verilog, System Verilog, coverage assertions, Debug, Ethernet based protocols, VCS simulation flow, Otn, Uvm, VMM, AXI memory controllers, adversarial testing

code coverage , perl, Regression Testing, Ovm, Ethernet Protocols, Python, multiple RTL simulators, X-propagation, Uvm, systemverilog, functional coverage