power optimization , Noc, Networking, Cpu, Perl, Verilog, System Verilog, Python, Tcl, LINT, High-Level Synthesis, cdc, power analysis, Peripheral Subsystems, Formal Verification Methodology, Shell-scripting, Synthesis, Timing Closure, RTL Coding, Micro-architecture Development

Perl, Python, Tcl, Emulation, systemverilog, System Verilog Assertions

Linux, Perl, Python, Tcl, EM, LVS, IR analysis, Calibre, physical signoff flows, ERC, DRC, Parasitic Extraction, Cadence Virtuoso

Perl, Verilog, Python

Nvme, DDR, Pcie, Verilog, System Verilog, Uvm, code coverage analysis, Axi, functional coverage coding, RTL debugging, scoreboard assertions, AHB

synopsys primetime , Python Scripting, Design Compiler, SDC constraint authoring and management, Physical-aware synthesis flows, Fusion Compiler, Formality, Physical-Aware Synthesis, STA PrimeTime

C, DDR, Pcie, Memory Consistency Models, verification components, Clock and Power Controllers, Caches, Coherency, Uvm, Security, systemverilog, Packet Processors, Hierarchies, standard verification methodology, LPDDR, Interconnect Protocols

VMware, Elk, PowerShell, Bash, Windows, Ms Azure, Gcp, Linux, Nagios, Virtualization, Python, AWS, Hyper-V, Checkmk