Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

analog circuits , Circuit Design, Custom Layout, Mentor, LVS, Physical Verification, EDA Tools, DRC, Synopsys, Cadence Virtuoso, Layout Design, Siemens tools

Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts, DRC LVS ERC and PEX, advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, FinFET advanced-node layout, lower-node technologies

manufacturing processes , Calibre, Analog Layout, Cadence Virtuoso XL, Design for manufacturability, Signal integrity analysis, Parasitic Extraction

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

shielding , matching , Dac, Routing, EMIR verification, ADC, PEX, floorplanning, Cadence Virtuoso Layout XL, LVS, Pll, Analog Mixed-Signal Layout Design, advanced technology nodes, SERDES, ERC, Placement, DRC, Op-Amp, LDO, Bandgap, GXL

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Routing, Pvs, PERL, Tcl, R3D, PEX, LVS, Layout Techniques, Verification, Skill Programming, CAD Tools, Calibre, Analog Layout, ERC, VCAR, DRC, VSR, virtuoso