Perl, Python, Design Verification, Verification methodologies, SV, DFT Engineering, Post Silicon Testing, Uvm, Automation flow development

Verilog, Jtag, Dft, MBIST, IEEE1500, IEEE1687, ATPG, Cadence

DFT architecture, ATPG setup, digital design fundamentals, hierarchical DFT methodologies, silicon bring-up, JTAG simulation, SCAN solutions, DFT scripting automation, post-silicon debug

Tcl, Verilog, Python, Jasper, Perl, Scan Insertion, VHDL, Memory Test methodologies, ATPG, Xcelium, Genus, Modus

Tcl Scripting, Jtag, Perl, Sta, MBIST, Scan insertion techniques, Test structures for DFT IP Integration, Test mode timing constraints, ATPG, Fault Models, Post-Si ramp up and debug on ATE, Coverage improvement techniques, SDF based simulations, Insertion verification on RTL Netlist level, Scan, Memory BIST generation, Physical Design, Test point insertion, Gate level simulations

Tcl Scripting, Python Scripting, primetime, StarRC, Formality

Logic Design, Synopsys, MBIST OCC validation flows, IEEE 1687 IJTAG standards, Digital Circuit Design, Scan insertion and ATPG tools, Hierarchical DFT and SDC constraint management, SpyGlass DFT rules, Mentor, Sta, Cadence, DFT for complex ASIC SoC designs, SSN design, Physical design flows, RTL design synthesis