architecture-level validation, DFT concepts, SoC Design Verification, MBIST, UVM testbench development, systemverilog, ATE functional patterns, reset boot flows, x86 processor-based SoC IP DV, Scan, DV sign-off, post-silicon debug, SerDes loopback IO validation, functional coverage

protocol analyzer , micro architecture , C, Gpu, Python, Logic Analyzers, Isp, Oscilloscopes, SoC validation, Display IP, DPU, Validation Test plan, HDDs, DP, FPGAs, Lauterbach debuggers, PRDs, dsi

architecture-level validation, DFT concepts, SoC Design Verification, MBIST, UVM testbench development, systemverilog, ATE functional patterns, reset boot flows, x86 processor-based SoC IP DV, Scan, DV sign-off, SerDes loopback IO validation, functional coverage

display technologies , Python Programming, Functionality, Bit Depth Color, OS Ecosystems, MIPI DSI-2, Bitstream Verification, Introspect SV series systems, Scaling Processing, FPGA Prototyping, PVT Testing, Frame Buffer, Lab Instrumentation, Pixel Formats, SV UVM, Continuous Integration tools, Low-Level Software