synopsys primetime , Tcl, Shell scripting, Python, Perl, clock skew, place-and-route, Synthesis, timing exceptions, jitter, ECO implementation, MMMC timing analysis

block subchip level place and route for SoC, ASIC Design, Physical Design, constraints synthesis

redhawk , Pvs, Python Scripting, Tcl, Perl, Innovus, Starrcxt, Calibre, QRC, ICC2, Physical Design, primetime, Tempus, Voltus

redhawk , Tcl, Perl, Deep sub-micron designs, Dc, Synthesis, Timing Closure, Pt, LVS, ICC, VSLP, Logic equivalence checking, Low Power checking, Calibre, STA timing, Formality, Place And Route, DRC, Physical Design, SOC design

static timing analysis, Digital Logic Design, Perl, Verilog, Python, Scripting, Tcl, Synthesis, memory subsystems, cdc, SOC design, Uvm, IP integration, systemverilog, Rtl Design, Axi, formal verification, EDA tool flows, LINT, Microarchitecture, Verification, bus architectures, automation of design flows

Computer Architecture, C, Perl, Verilog, System Verilog, Python, Vlsi, CAD, Chip Floorplan, Power Distribution, Timing Closure, Physical Design Methodologies

clock distribution , C, Computer Architecture, Verilog, System Verilog, Python, Perl, Power Distribution, Asic Physical Design, Tool Development, chip floorplan, Vlsi, CAD, floorplan SOC planning, physical design methodologies, Timing Closure