PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Unix, Perl, Linux, Shell scripting, Python, Tcl, Place Route Cadence Innovus, Physical Verification Calibre DRC LVS, IR EM Cadence Voltus RedHawk, STA Cadence Tempus

synopsys tools , Tcl, Python, Linux, Sram, Memory compilers, primetime, Cadence Virtuoso, Design Compiler, Spectre, Hspice, Rom

Fpga, Logic Design, Verilog, Uvm, Timing Constraints, TCL scripts, regression frameworks, Timing Analysis, Power product design, System-Verilog, RTL Coding, Functional Verification, Sta, micro-architecture, ATPG generation, formal verification, synthesis scripts, Synthesis, ABV, design constraints, Digital Verification, Scan Insertion