Pcie, Perl, Python, System Verilog, Tcl, CHI, SMMU, assertion-based verification, Uvm, Coresight, Axi, coverage-driven testing, CXL, SVA

DDR, Pcie, Verilog, Ethernet, Python, Cadence Incisive, UCIe, Uvm, Synopsys VCS, formal verification, VHDL, Modelsim

Verilog, Asic verification, formal verification, power-aware verification, gate-level verification, Uvm, systemverilog

semiconductor ip , Silicon Validation, systemverilog, Uvm, SOC design, ip design, Simulation, Emulation, Dft, Design For Testability, Ate, Semiconductor, semiconductor design, Design Verification

Shell, C, Perl, Verilog, Python, Tcl, EDA Tools, UVM methodology, systemverilog

React, Graphql, Gcp, Automated Testing, Node.js, Python, AWS, Microservices, AI-assisted development tools

Numpy, Git, Pandas, Pytorch, Version Control Systems, Python, machine learning frameworks, OpenAI’s GPT models, Hugging Face, data processing libraries, prompt engineering

Django, PostGreSQL, Gcp, Python, dbt