C, Verilog, Perl scripting, Python, Axi, Uvm, AHB, systemverilog

C, Python, LabVIEW, Analog Digital and Mixed-signal validation lab equipment, signal generators, SMUs

Usb, C, Uart, Bash, Spi, Pcie, Perl, Verilog, I2c, System Verilog, Python, Tcl, gate-level simulations, verification methodology, i2s, Uvm, DP, Sd

Python, Jasper VC Formal, formal verification, Property-based FV, Formal Tools, SVA, Questa Formal

Python, systemverilog, Analog Mixed-Signal circuits, EDA Tools, Verilog-A, Cadence

test environments , scoreboard , C, Soc Architecture, Shell, Verilog, Test Cases, Sequencers, Mixed signal designs, Debugging RTL and Gate simulations, Industry-standard simulators, Agents, Revision control systems, Verification testbenches, Testbenches, Regression systems, Verification methodology, Directed and constrained random verification methodology, Monitors

Perl, Python, Tcl, DRC and LVS debugging, Calibre ICV, CAD and EDA tool development, Mentor Graphics, Cadence, Synopsys