power integrity , Shell, Perl, Python, Tcl, Physical Design signoff, Ansys RedHawk, IR EM analysis, Cadence Voltus

power integrity , Routing, Perl, Python, Tcl, OCV, CTS, primetime, Timing Constraints, EM IR awareness, floorplanning, SI Crosstalk, Full-Chip STA, CRPR, Cadence Tempus, SDC, Eco, MMMC, Physical Design, POCV, Clock Architecture, LVF, AOCV

Wireshark, Zigbee, Wlan, Thread, Python, Iperf, Ellisys sniffers, Bluetooth BR, LE Audio

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

synopsys primetime , Synopsys FusionCompiler, Timing Signoff Tools, Physical Design Flow, SDC Proficiency, AI ML Integration, Advanced Node Experience, Advanced Clocking