static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

boundary scan , Perl, Verilog, Python, Tcl, SOC design, Cadence Xcelium, Siemens Tessent, ATPG generation, Cadence Genus, IJTAG integration, Siemens Questa, Dft, fault coverage analysis, Scan Insertion, Scan Architecture, VHDL, ASIC, JTAG implementation, MBIST insertion, Synopsys TetraMAX, DFT DRC closure

Apache Flink, Gcp, PostgreSQL, Apache Spark, OLAP, Python

Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2

Apis, Node.js, Microservices, Angular, Testing Frameworks, Typescript, Javascript, System Design, CI CD, service-oriented architecture, Object-Oriented Design, observability

.NET, .Net Core, Github, T-sql, Ms Sql Server, Kafka, Grafana, Microservices, Nosql, Octopus, Docker, Teamcity, Postgres, Visual Studio, Resharper, Azure, Kubernetes, MS Copilot, Event-driven, ChatGPT, Rancher, AMQ, Rider, CQRS, GitHub Copilot, ASP.NET Core