Python, scoreboarding, Mentor Questa, Cadence Xcelium, AXI protocol, SystemVerilog UVM, GLS, Synopsys VCS, memory controller architecture, assertions SVA, DDR protocol JEDEC specifications, functional coverage

Ethernet, Pcie, Synopsys, Uvm, advanced verification methodologies, systemverilog, Mentor, Cadence, PAM4, Register modeling, D2D, protocol VIP integration, Avery, PAM2

Shell, Pcie, Perl, Arm, Python, Tcl, MCU, AMBA, Axi, UCIe, systemverilog

cache coherency , Vcs, Perl, Python, Tcl, CHI, Ace, Xcelium, GPU Verification, AMBA protocols, NoC Integration, coverage-driven verification, SystemVerilog UVM, constrained-random verification, Performance Validation, Axi, Questa, SVA assertions