memory controllers , Uart, Spi, FPGA Design, Pcie, Verilog, I2c, System Verilog, Microsemi, Ethernet based protocols, Unix system, Otn, Uvm, quartus, Axi, VHDL, Vivado, VMM, RTL Coding, Libero, Xilinx, Altera

Uart, Spi, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Microsemi FPGAs, Uvm, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Uart, Spi, FPGA Design, Hdl Languages, Pcie, Verilog, I2c, System Verilog, Ethernet based protocols, Unix system, Otn, Uvm, Microsemi FPGAs, quartus, VHDL, Vivado, VMM, AXI memory controllers, Libero

Pcie, Systemc, Jenkins, Python, Perl, MATLAB, Design Verification, DV, Design Verification Lead, IP Verification, Subsystem Verification, systemverilog, Uvm, formal verification, Functional Verification, Constraint Random, Coverage Closure, Verification Plan, Specman E, Xcelium, Vmanager, Verilog-A, RNM, C Modelling, ISO 26262, Semiconductor, Pre-Silicon Verification

flash translation layer , Embedded Firmware, Test Plans, Linux Operating System, Python, AI tools, Back End NAND Media management, Lecroy JDSU analyzers, SSD Product Validation, Automated test environment, NVMe Protocol, PCIe-CV test suites, IO workloads

SerDes architecture, EMIB, IBIS-AMI, crosstalk budgeting, InFO, eye diagram closure, advanced packaging, CoWoS, S-parameter analysis, Signal Integrity, UCIe integration, PCIe architecture, Hspice