About Marvell

Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.

At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.

Your Team, Your Impact

As a Design Verification Senior Principal Engineer with Marvell, you'll be a member of the Central Engineering business group. If you picture Marvell as a wheel, Central Engineering is the center hub providing IP to be used by all the other spokes on that wheel, including Automotive, Storage, Security, and Networking. You'll be part of a digital team of about eight people making a big impact on this organization, working on ultra-dense and performance Static Random Access Memory (SRAM) memory compilers.

This team hires some of the biggest problem solvers in Silicon and has a huge impact on the work done at Marvell. The customers served by this team are often other chip companies and big tech companies, familiar names to all candidates.

What You Can Expect

Define and drive improvements in DV processes for efficient and high-quality execution
Collaborate with IP, Subsystem, and SoC teams on test plan creation, testbench architecture, and milestone reviews
Work closely with Design and DV teams across IP, Subsystem, and SoC levels for test plan - development, execution, debug, coverage closure, and gate-level simulations
Coordinate with cross-functional teams including Architecture, Chip Lead, Emulation, and Program Management to drive Subsystem-level DV execution
Partner with Silicon bring-up and Firmware teams to support post-silicon validation and bring-up activities
Own and debug simulation failures to identify and resolve root causes
Architect and implement simulation testbenches using UVM & C.
Develop and execute test plans to verify design correctness and performance
Collaborate with logic designers for thorough verification coverage

What We're Looking For

Master's/Bachelor's degree with 18+ years of relevant experience.
Lead End-to-End Subsystem DV execution and sign-off
Experience in leading core technical project deliveries in design verification at Subsystem level.
Experience in coding UVM Subsystem/block level testbenches, BFM, scoreboards, monitors, etc.
Good knowledge of ARM architecture and AMBA bus standards like AXI-4, CHI and ACE.
Experience with industry-standard interfaces such as DDR/HBM/PCIE/Ethernet/USB.
Proficient in writing and debugging tests in UVM as well as C.
Proficient in using Cadence, Synopsys, Mentor and/or ARM verification tools.
Nice to have experience with assertion-based formal verification tools.
Proficient in programming in scripting languages such as tcl and Perl. Understanding of hardware emulation support.
Experience in version control tools like GIT, SVN etc

Additional Compensation And Benefit Elements

With competitive compensation and great benefits, you will enjoy our workstyle within an environment of shared collaboration, transparency, and inclusivity. We're dedicated to giving our people the tools and resources they need to succeed in doing work that matters, and to grow and develop with us. For additional information on what it's like to work at Marvell, visit our Careers page.

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.

Interview Integrity

To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.

These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.

This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.

Senior Principal Design Verification Engineer