C, Embedded C, Perl, Debugging, Python, Tcl, CPU architecture, CPU validation, complex system debug, coherent fabric, bare metal programming, Embedded Operating Systems, CPU uArch

Excel, Python, Ms Word

Unix, Lsf, Jenkins, Git, Shell, Linux, Verilog, Gitlab, Python, Tcl, Synthesis, cdc, Simulation, RTL, make, systemverilog, RDC, UGE, LINT, Low Power, Slurm

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management

Numpy, Git, Pandas, Pytorch, Version Control Systems, Python, machine learning frameworks, OpenAI’s GPT models, Hugging Face, data processing libraries, prompt engineering

Python, PERL, Debugging, Silicon Validation, analog simulation, silicon bring-up, Analog Circuit Design, noise analysis, stability and compensation, CMOS technology, device mismatch and variation, virtuoso

protocol analyzer , Python, Firmware Development, Silicon bring-up, Debug tools, Oscilloscope, JTAG debugger, Validation, Product characterization, Lab equipment

Unit Testing, Tcp, C++, Data Structures, Http, Python

usb3.0 , Sata, Python, Ddr3, LabVIEW, MIPI-MPHY, Clock and timing sources, Electrical engineering fundamentals, Oscilloscopes, PCI-e, High Speed Digital IP Modules, Bench Test Setup, characterization, Controller based SOCs, CSI, SW macros, Spectrum analyzers, USB2.0, Lab Automation tools, FPGA Design Tools, Post Si Validation, signal generators, Xilinx, ddr2, MIPI-DPHY, Altera