static timing analysis, Perl, Verilog, Python, Tcl, Rtl Design, Synthesis, Dft, ATPG, systemverilog

Ecos, Perl, Python, Tcl, FC PrimeTime, Sta, Design Compiler, CTS, EM, physical signoff, Ir, advanced-node SoCs, congestion optimization, ASIC Physical Design Full-Chip Implementation, MCMM, design closure, low-power implementation, PPA trade-offs, Synopsys ICC2

Rtl Design, high-speed interfaces, thermal monitoring integration, power management, clock-gating, micro-architecture, systemverilog, embedded microcontroller integration, reset-domain architecture

Git, Bitbucket, Verilog, Visualstudio, Python, System C, Uvm, systemverilog

Perl, Verilog, Python, spyglass, VHDL, DDR memory controllers, PCIe protocols

UNIX, Verilog, System Verilog, Debugging, Windows, Automated flows for generating RTL, Digital IP development