power integrity , Perl, Python, Tcl, FinFET process technologies, Ansys RedHawk-SC, Quantus PrimePower, Cadence Voltus, physical-design implementation, Joules, EMIR analysis, StarRC, current and activity models

DDR, Usb, Pcie, Ethernet, SV, CXL, Uvm

System Verilog, Systemc, UVM based verification, ARM bus protocols

AI ML techniques, Uvm, systemverilog, Coverage-driven verification

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, verification platforms, transaction level modelling, test bench infrastructure, formal verification methods, emulation platforms

Tcl, Python, Perl, systemverilog, System Verilog Assertions, Emulation

C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Perl, Python, Tcl, Logic Synthesis, Physical-Aware Synthesis, PPA optimization, systemverilog, UPF management