MATLAB, Python, post-layout extraction, layout techniques, ADE, Monte Carlo analysis, CMOS analog design, Spectre, mixed-signal IC design, Cadence Virtuoso, Verilog-A modeling, corner simulations

DFE, Duty Cycle Correction, BGR, Oscillators, High-speed clock distribution, Rx CDR, Tx Serializer Output Driver, CTLE, Generic Analog Circuits, Analog Circuit Design, EDA Tools, Bias Circuits, Deserializer, Circuit design simulation and analysis, LDO, Lower Nodes Experience, Amplifiers, VGA, Comparators, Power Management Circuits, High-Speed SerDes Tx and Rx blocks

UNIX, signals systems and transforms, AC DC analysis, circuit simulation tools, MOS transistors, High Volume Manufacturing, feedback systems, end-to-end design flow, poles zeros compensation, layout tradeoffs, Analog Circuit Design, Mixed Signal Design, Modeling Tools, layout verification tools, CMOS Bi-CMOS fabrication processes, loop dynamics, device physics

chip top-level ownership, Virtuoso Cadence, reliability simulations, silicon debug expertise, Analog Circuit Design

Spectre, Analog Design, Cadence Virtuoso, Post layout parasitic back-annotation

Cadence Virtuoso, analog and mixed-signal circuit design, high-speed analog architectures, Signal Integrity, jitter, Spectre, advanced CMOS technology nodes

System integration, Thermal Performance, Testing Methodologies, noise reduction, Analog circuit simulation, Memory Design, Signal Integrity, Prototyping techniques