physical closure, Synopsys, top-level memory integration, decoders, memory compiler IPs, bit-cell arrays, Sram, LVS, collaboration with circuit design, layout experience, sense amplifiers, power performance, yield manufacturability, verification PDK methodology teams, Cadence, optimize layouts for area, IR EM challenges, density verification, FinFET design rules, DFM guidelines, memory periphery, DRAM, DRC, layout and physical verification tools

cadence schematic capture , Chip Integration, RC requirements, Electro Migration, LVS, Antenna, Virtuoso Layout, Physical Verification, AI layout automation, Calibre, Cadence Tools, Memory Architecture, floor-planning, hierarchy layout, memory layout design, ERC, Layout XL, DRC, SKILL programming, Hercules