Machine Learning, Eda, Automation, Shell, Perl, Python, Tcl, CAD, Ai, RTL-to-GDSII flows, Physical Design, EDA Tools, Silicon Engineering

Fpga, Perl, Python, low power verification, Uvm, systemverilog, AMBA bus protocols, Baremetal processor environments, RTL development environments, verification platforms, transaction level modelling, test bench infrastructure, formal verification methods, emulation platforms

Synopsys, MBIST, physical design flows, Synthesis, test-mode integration, ATPG, DFT ATPG tools, cdc, Dft, Rtl Design, Scan Insertion, Cadence

Process Development, Strategic Thinking, Negotiation, Custom Synthesis, Contract Manufacturing, Market Intelligence, Stakeholder Management, Business Development

SDWAN, Cisco Aci, Solarwinds, Gcp, Perl, Cisco Ise, Ipsec Vpn, Python, AWS, Sdn, Cisco SDA networks, Cisco firewalls, SD-LAN, Cisco DNAC suite, cloud solutions deployment and support, Cisco Wi-Fi, 1000Eyes, network analysis tools

Sql, Generative AI, Dubbing, Product Management, Video Audio Generation, Voice Synthesis

.NET, Maven, PowerShell, Artifactory, Ibm Rational Clearcase, Npm, Git, Msbuild, Perl, Azure DevOps Server, Python, TFVC, Azure Artifacts, medmake, NuGet, omake, CI CD pipelines

Perl, Python, Tcl, SoC DFT architecture and design

smartsheet , JIRA, Confluence, Silicon Validation, STA Signoff, VLSI SoC chip design lifecycle, Physical Design, Rtl Design, Microsoft Project, Program Management, Design Verification, Dft

static timing analysis, Debugging, Octave, MATLAB, Logic Design, Shell, Verilog, Python, Tcl, place-and-route, Configuration Version control tools like SVN, RTL design in VHDL, XSIM, Xilinx tools for synthesis and implementation, Synthesis, Hardware Design, Zynq SoC, Zynq UltraScale plus, constraint management, Modelsim