C, Python, LabVIEW, Analog Digital and Mixed signal IPs, DMM, Oscilloscopes, Bench Characterization, signal generators, SMUs

Debugging, Scripting, formal verification, assertions, hardware micro-architecture, testplans

Mac, Switch, Pcie, 1G Ethernet, UFS, SV, XUSB, High Speed IO verification, verification tools for simulation and debug, Uvm

C, Verilog, Scripting, RTL testbench debug, interconnects, memory hierarchy, Arm-based SoC architecture, Uvm, UPF, systemverilog, coverage closure, coherency

Verilog, System Verilog, CPU architecture, Coherent fabric designs, debugging skills, ARM knowledge

bandwidth management , Machine Learning, Artificial Intelligence, Microprocessor Cores, industry-standard simulators, hierarchical memory subsystems, Specman E, Debug, IP subsystem SoCs, interconnects, regression systems, congestion control, systemverilog, vector processing units, revision control systems, full verification life cycle, packet processing, constrained-random verification environments, AI ML Accelerators, Verification, standard IP components