MATLAB, Python, post-layout extraction, layout techniques, ADE, Monte Carlo analysis, CMOS analog design, Spectre, mixed-signal IC design, Cadence Virtuoso, Verilog-A modeling, corner simulations

Cadence Virtuoso, Mixed-Signal IC Design, High-Speed ADC Design, Analog IC Design

Matlab, Spectre, Process technologies, Analog Circuit Design, Architectural tradeoff analysis, Monte Carlo analysis, AMs, Signal grounding, device physics, Schematic generation, Physical layout management, Block level topology selection, Post layout parasitic extraction, Simulation on modern CAD tools, Die area optimization, Simplis, Routing tradeoffs, Simulation verification, Top level simulation, IC system partitioning, Cadence tool set, Worst case identification

UNIX, Layout tradeoffs, End to end design flow, CMOS BiCMOS fabrication processes, Modeling Tools, MOS transistors, Analog Circuit Design, Poles zeros compensation, Signals systems and transforms, Mixed Signal Design, Production test applications, Feedback systems, device physics, Circuit simulation tools, AC DC analysis, Loop dynamics, Analog Power IC design, Layout verification tools

Programming, Analog IC design, Synopsys, Mixed-signal IC design, Cadence

system integration, converter-level architecture, switching regulator circuits, DC-DC converters, Spectre, control-loop concepts, post-Silicon debug, analog mixed-signal IC design, extraction verification tools, design bring-up, Cadence Virtuoso, top-level analog simulations, high-voltage designs