Power gating and retention strategies, Signal Integrity Analysis, Power Planning, ASIC SoC physical design, Leakage optimization and dynamic power reduction, UPF CPF-based low-power implementation flows, Timing Closure, Physical Verification and Signoff, Advanced low-power architectures, Clock gating methodologies, Adaptive power management techniques, Floor planning and Partitioning, Power-aware physical design and implementation closure, Placement and Optimization, Routing and Congestion Analysis

Jenkins, Devops, Git, Docker, Kubernetes, Python, AgenticAI frameworks, R, AI ML engineering, CI CD tools

Java, Ml, C, Microservices, Python, Kubernetes, cloud-native systems, LLMs, Go, Ai, Tetragon, eBPF, Zero Trust

Kvm, C, Microsoft Sql Server, Redis, Debian, Rabbitmq, Pytorch, Linux, Docker, MySQL, MongoDB, Python, scikit-learn, LightGBM, Consul, ONNX, libvirt

flash translation layer , Embedded Firmware, Test Plans, Linux Operating System, Python, AI tools, Back End NAND Media management, Lecroy JDSU analyzers, SSD Product Validation, Automated test environment, NVMe Protocol, PCIe-CV test suites, IO workloads

Git, Visual Studio, Agile Development, Python, Board-level debugging, RapiTest, Hardware software integration, Wind River VxWorks

Multi-voltage domains, Physical design methodologies, Physical Verification, Power gating, PDN IR signoff, ASIC design flows, DDR PD expertise, 3DIC, Physical Design, Bump Spec understanding, RDL-design, PPA optimization, PCIE-high speed interface