advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, DRC LVS ERC and PEX, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts

Analog and Analog Circuits fundamentals, Circuit Design concepts, Layout Design for standard cells, CMOS process design rules

Schematic layout tools, Technical reports and communications, Design FMEA creation and revisions, Analog and digital design, Test plans and test reports

Shell, Perl, Python, Tcl, Samsung 3nm, Cadence Layout XL, Register File Layout, Synopsys Custom Compiler, Calibre DRC, Samsung 4nm, TSMC 5nm, Skill, High-Density Memory Arrays, TSMC 2nm, Memory Compiler Layout, Memory Layout, Calibre PEX, Multi-Patterning Requirements, SRAM Layout, Calibre LVS, Cadence Virtuoso, ROM Layout, FinFET Technologies

FD-SOI technologies, Calibre, Latch-up prevention, Analog Mixed-Signal IC Layout, Substrate isolation, GF22FDX

power converters , post layout parasitic extraction, Monte Carlo analysis, bandgaps, sensing circuitry, Simulation, block level topology selection, Spectre, switching regulators, schematic generation, DACs, charge pumps, VHDL, Amplifiers, Mixed Signal Design, physical layout management, Spice, Analog Design, Transistor Level Design, Comparators, IC CAD tools, precision analog control

Analog power product testing, Pcb Layout, Multimeters, Testing and collecting data on IC chips or circuits, Debug troubleshooting, High current testing, Oscilloscopes, ATE test development, Spectrum Analyzers