advanced matching and layout techniques, Cadence Virtuoso Custom Compiler, DRC LVS ERC and PEX, FinFET advanced-node layout, lower-node technologies, Analog Mixed-Signal Layout, MOS resistor capacitor current mirror differential pair and analog IP layouts

shielding , DC-DC Converters, Common-centroid layout, PEX, BCD Bipolar-CMOS-DMOS technology, LVS, Interdigitated structures, Calibre, Latch-up prevention, Analog layout techniques, Buck Converters, ERC, DRC, ESD-aware layout practices, Cadence Virtuoso, Guard rings, Device matching, Symmetry

Synopsys IC Validator, Calibre DRC LVS PEX, high-speed analog and mixed-signal layout design, Custom Compiler, LVS, Cadence Pegasus, DRC, Cadence Virtuoso Layout Suite, ERC checks, 7nm FinFET technology

analog circuits , Circuit Design, Custom Layout, Mentor, LVS, Physical Verification, EDA Tools, DRC, Synopsys, Cadence Virtuoso, Layout Design, Siemens tools

manufacturing processes , Calibre, Analog Layout, Cadence Virtuoso XL, Design for manufacturability, Signal integrity analysis, Parasitic Extraction

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

shielding , ESD latch-up prevention, Analog Custom Layout Design, Guard rings, TI Texas Instruments project environment, Cadence Virtuoso, Matching symmetry, Layout verification tools, Common centroid, Advanced process nodes foundry rules, DRC LVS ERC EM IR checks

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies