shielding , DC-DC Converters, Common-centroid layout, PEX, BCD Bipolar-CMOS-DMOS technology, LVS, Interdigitated structures, Calibre, Latch-up prevention, Analog layout techniques, Buck Converters, ERC, DRC, ESD-aware layout practices, Cadence Virtuoso, Guard rings, Device matching, Symmetry

manufacturing processes , Calibre, Analog Layout, Cadence Virtuoso XL, Design for manufacturability, Signal integrity analysis, Parasitic Extraction

ICValidator, SOI, LVS, Mentor Graphics, Analog layout design, TSMC PDKs, Calibre, Multiple layout design environments, Synopsys IC Compiler, TSMC 7nm, Cadence Virtuoso, DRC, Parasitic Extraction, Statistical analysis tools, FinFET, Mixed-signal layouts, Low-power design techniques

matching , Bandgap Oscillators, xACT, LVS, EM, IR drop, Cadence Tools, parasitic effects, MXL, reference circuits, LVS DRC PEX EMIR verification flows, Quantus, GXL, EXL, Xl, Voltus, Calibre DRC, LDOs, StarRC

analog layout concepts, Mentor Calibre, Cadence Virtuoso XL, FinFET technologies

Dac, Full Custom Analog Layout, Analog Mixed-Signal Layout, RF Layout, Pll, LNA, mixers, VCO, ADC, Cadence Virtuoso XL, Cadence Virtuoso GXL, Calibre, DRC, LVS, ERC, Antenna Checks, Device Matching, Symmetry, Common Centroid, Interdigitation, Physical Verification, Layout Closure, Advanced Process Nodes

Cadence Tools, FinFET process technologies, DRC LVS checking flows with Calibre