C, Fpga, Python, Perl, Uvm, RTL, AMBA bus protocols, systemverilog, Emulation platforms, Automation scripts, Transaction level modeling

Verilog, Ethernet, Python, Pcie, DDR, Modelsim, Synopsys VCS, VHDL, UCIe, Uvm, formal verification, Cadence Incisive

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM

Usb, Ovm, Soc, DDR, Pcie, Ethernet, System Verilog, Ip, Uvm, Video, MIPI, VMM, ARM Based SoC Verification, HDMI, dsi, CSI

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Assertion checkers, Uvm, MIPI, Validation plan, System Verilog HVL, Coverage and scenario creation, VMM Test Harness

C, Verilog, Scripting, coverage closure, verification flows, RTL testbench debugging, memory hierarchy, AMBA protocols, Uvm, systemverilog

Usb, DDR, Shell, Pcie, Perl, Ethernet, Python, CHI, Ace, RISC-V, ARM CPU, Uvm, systemverilog, Axi, CXL, SVA

Usb, System Verilog, Jtag, Ethernet, Python, Pcie, Perl, TSN, UVM methodology, SoC architecture verification, scripting in Linux Unix environments, High speed USB, Design for Debug, ARM based SoC verification