DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet

Pcie, Ovm, Axi, AMBA, CHI, Ace, interconnect and bus protocols, cache coherency concepts, CXL, Uvm, systemverilog

Vcs, Shell, Perl, Python, PCIe Gen5, Xcelium, Uvm, systemverilog, AMBA, Axi, APB, Questa, CXL, AHB, SVA

Spi, I2c, Gpio, Uart, Pcie, DDR, UVM methodology, I3C, QSPI, CXL, systemverilog, HBM

cache coherency , Uvm, DMA engines, ARM-based SoCs, memory systems, systemverilog, Transaction-level verification, CHI, Ace, AXI NoC architectures

code coverage , Nvme, System Verilog, Ethernet, Pcie, DDR, Uvm, UCIe, simulation and debug tools, AHB, assertions, functional coverage, CXL, APB, Axi

Usb, Ovm, Pcie, Ethernet, Test and coverage plan, Verification environment, Coverage, Assertion checkers, Uvm, MIPI, VMM, Validation plan, System Verilog HVL, Scenario creation

Vcs, System Verilog, Ethernet, Pcie, Git, RISC-V CPU subsystems, Questa, Uvm, UPF, cdc, AMBA, level shifter implementation, clock reset architectures, AHB, C Language, low-power verification techniques, APB, Axi, power management strategies, FIFOs

IP SoC verification, ASIC-SoC design verification, systemverilog

Usb, Jtag, Pcie, Perl, Ethernet, Python, System Verilog, UVM methodology, Design for Debug, scripting in Linux Unix environments, SoC architecture verification, TSN, ARM based SoC verification, High speed USB