Search Jobs
Search by job, company or skills
Search by job, company or skills
POSITION TITLE: Senior Engineer/Engineer – ASIC Design Verification
LOCATION: Noida/ Bangalore/ Hyderabad/ Pune/ Chennai/ Ahmedabad
ROLE & RESPONSIBILITIES
An expert level with developing UVM-based SV test-benches.
Highly experienced with defining block, sub-system and SOC top level test plans.
Relevant experience with one or more of PCIe, NVMe, NAND, DDR and CPU sub-systems.
Deep understanding and knowledge of verification methodologies, flows and quality metrics
The incumbent will be responsible for executing complete verification project in the role senior engineer with hands on experience, mentoring, client communication / interactions, in-depth technical reviews, and close tracking of technical as well as management aspect
ESSENTIAL SKILLS & EXPERIENCE
At-least 4 years of experience in System Verilog HVL.
At-least 3 year of experience in OVM/UVM/VMM/Test Harness.
Hands on experience of developing assertion, checkers, coverage and scenario creation.
Must have executed at-least 1 SoC Verification project
Experience in developing test and coverage plan, Verification environment and validation plan.
Knowledge of at least one industry standard protocols like Ethernet, PCIe, MIPI, USB or similar is required.
EDUCATION BACKGROUND
B.E./ B.S./ B.Tech/ M.S./ M.Tech in VLSI/Electronics/Electrical/Computer/Instrumentation Engineering.
Job ID: 95328213
Skills:
simvision , Shell, Vcs, Python, Tcl, Verdi, Xcelium, QuestaSim, Uvm, systemverilog
Skills:
DDR, Pcie, Ethernet, SRIO, RDMA, verification of ARM RISC-V based sub-systems or SoCs, IP or integration verification of high-speed interfaces, Design Verification, ROCE, RDMA TSO, automated flows and scripts for data exploration analysis and performance verification, 400G Mac, LRO, Congestion Control, waveform debugging tools, PSP, Simulators, SV Assertions, HBM, Formal Emulation, UVM based verification environments, RDMA over converged Ethernet
Skills:
Pcie, Ovm, Axi, AMBA, CHI, Ace, interconnect and bus protocols, cache coherency concepts, CXL, Uvm, systemverilog
Skills:
Computer Architecture, Verilog, Uvm, systemverilog, coverage-driven verification, advanced stimulus generation
Skills:
Makefile, Perl, Ruby, Python, object-oriented programming, simulation debugging, power aware simulation, ASIC verification tools, Uvm, systemverilog, C-DPI, Axi, AMBA, linting, AHB
We don’t charge any money for job offers
