Perl, Tcl, Skill, EDA Tools, Cadence Virtuoso

PERL, Python, Tcl, Sta, RTL-GDS flows, Physical Verification, SNPS CAD Flow, SNPS CDNS-based tools

Tcl Scripting, Python, Synopsys DFT flow, Tool installation configuration, Dft, PrimePower, Virtuoso SI2 scripting, virtuoso, LEC, Voltus RedHawk, Power and signoff flow automation

FEA tools, Debugging, Control loop theory, PCB CAD tools, power management, Board level analog and digital circuit design, Circuit Design, Data analysis using Excel or JMP, PCB schematic design, Troubleshooting

Jtag, Perl, Verilog, Python, Tcl, Sta, MBIST, Siemens Tessent, Synopsys TestMAX, systemverilog, DFT Compiler, Scan Insertion, Physical Design, Cadence Modus, RTL synthesis, ATPG, Scan Compression, DFT Architecture

Python, Tcl Scripting, Dft, LEC, Virtuoso SI2 scripting, Power and signoff flow automation, Tool installation configuration, Synopsys DFT flow, PrimePower, Voltus RedHawk, virtuoso

synopsys tools , Tcl, Python, Linux, Sram, Memory compilers, primetime, Cadence Virtuoso, Design Compiler, Spectre, Hspice, Rom