Staff Engineer – DFT (Design for Test)
Location: Bengaluru, India
Experience: 8–12 Years
About the Role
We are seeking a Staff DFT Engineer to architect and deliver robust DFT solutions for next-generation SoCs. You will own the DFT implementation flow from architecture through silicon bring-up, working closely with RTL, Physical Design, STA, and Product Engineering teams.
What You'll Do
- Define and drive DFT architecture for complex SoCs.
- Implement and sign off Scan Insertion, MBIST, ATPG, Scan Compression, and JTAG/Boundary Scan.
- Generate and optimize ATPG patterns to achieve high fault coverage and test quality.
- Debug DFT issues across RTL, synthesis, physical implementation, and silicon.
- Collaborate with cross-functional teams to ensure DFT readiness and production success.
- Improve DFT methodologies, automation, and test efficiency.
What We're Looking For
- 8–12 years of hands-on ASIC/SoC DFT experience.
- Strong expertise in DFT Architecture, MBIST, ATPG, Scan Insertion, Scan Compression, and JTAG.
- Experience with Siemens Tessent, Synopsys TestMAX/DFT Compiler, or Cadence Modus.
- Good understanding of RTL, synthesis, STA, and Physical Design.
- Proficiency in Verilog/SystemVerilog and scripting (Python, Perl, or Tcl).
- Experience with advanced process nodes is a plus.
Qualification: Bachelor's or Master's degree in Electronics, Electrical Engineering, Microelectronics, or a related discipline.
