layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design

redhawk , Tcl, Perl, Deep sub-micron designs, Dc, Synthesis, Timing Closure, Pt, LVS, ICC, VSLP, Logic equivalence checking, Low Power checking, Calibre, STA timing, Formality, Place And Route, DRC, Physical Design, SOC design

power integrity , Routing, floorplanning, Crosstalk Analysis, Timing Optimization, Cadence Innovus, LVS, ECO Engineering Change Order, Signal Integrity Closure, Physical Verification, Physical Design, DRC, EMIR Analysis

Tcl, Python, PERL, Seahawk, Tempus, primetime, Innovus, ICC2

power optimization , Perl, Python, Scripting, Tcl, Mentor, Timing Analysis, Cadence, Physical Design, Signal Integrity, EDA Tools, Synopsys

Tcl, Routing, Perl, Netlist2GDSII Implementation, Power Integrity Analysis, primetime, Floor Planning, Physical Verification, Cadence Tools, Calibre, CTS, Innovus, Sta, ICC2, Physical Design Methodologies, Tk, Placement, PT-PX, sub-micron technology