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Role - Physical Design Engineer
Location - Bangalore, Hyderabad
Experience - 6+years
JD
• In-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification.
• Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl/Tk/Perl.
• Must have hands-on experience on Synopsys/Cadence tools. (Innovus, ICC2, Primetime, PT-PX, Calibre).
• Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environmentIn-depth knowledge and hands-on experience on Netlist2GDSII Implementation i.e. Floor planning, Placement, CTS, Routing, STA, Power Integrity Analysis, Physical Verification
• Should have experience on Physical Design Methodologies and sub-micron technology of 28nm and lower technology nodes.
• Should have experience on programming in Tcl/Tk/Perl · Well versed with timing constraints, STA and timing closure.
• Inspirational leadership style, good communication skills, and ability to work in a global environment.
Job ID: 145158805
Skills:
layout verification , Computer Engineering, System Verilog, Tcl, low-power designs, Electrical Engineering, Computer Science, design rules, Vlsi Design
Skills:
redhawk , Tcl, Perl, Deep sub-micron designs, Dc, Synthesis, Timing Closure, Pt, LVS, ICC, VSLP, Logic equivalence checking, Low Power checking, Calibre, STA timing, Formality, Place And Route, DRC, Physical Design, SOC design
Skills:
power integrity , Routing, floorplanning, Crosstalk Analysis, Timing Optimization, Cadence Innovus, LVS, ECO Engineering Change Order, Signal Integrity Closure, Physical Verification, Physical Design, DRC, EMIR Analysis
Skills:
power optimization , Perl, Python, Scripting, Tcl, Mentor, Timing Analysis, Cadence, Physical Design, Signal Integrity, EDA Tools, Synopsys
Skills:
redhawk , Tcl, Routing, Python, Perl, Multi-voltage domains, Foundry PDKs, UPF, Timing Closure, Signoff, Cadence Innovus, Power gating, floorplanning, primetime, Tempus, Synopsys ICC2, CPF, Voltus, Placement, Physical Design, Samsung, Low-power design techniques
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