Soc Architecture, Data Analysis, product test patterns, yield management system coding language, failure analysis techniques, database structure, yield enhancement techniques

Test Methodology, Silicon Validation, manufacturing debug, Advantest 93K, Smart Scale, ATE test development, Teradyne UFLEX testers, Dft, silicon process fundamentals, DFM concepts, yield analysis

Product Test Fab-Process, Wafer Fabrication Processes, Electrical and Physical Failure Analysis, Fault Diagnostic Capabilities, Semiconductor Device Physics, Yield Improvement

Test Methodology, yield analysis, UltraFlex test handler, Adventest 93K, quality management tools, debugging skills, wafer prober

Data Analytics, Silicon Characterization, Probe Coverage Strategy, Yield Analysis, device characterization

statistical data analysis , lithography tooling, project management, photolithography process, Fmea, Spc, Doe, cost yield improvement, Camline, process transfer, Jmp

Data Analysis, process correction, semiconductor manufacturing equipment, Fmea, process integration, Spc, FDC, Metrology, Analytical Methods, Process Support, Qualification, equipment setup, process tuning, operation, Optimization, Technology Transfer, Troubleshooting, Doe, yield improvement, defect analysis, root cause investigation

boundary scan , Sta, production test program, constraint development, structural test vectors, logical issues, Scan Insertion, low-power DFT architecture, MBIST, test coverage analysis, RTL, scan ATPG, Timing Concepts, DFT implementation, GLS gate level simulation, ATPG, MBIST test benches, simulation in pre post-layout environments