boundary scan , C, Perl, Verilog, System Verilog, Python, Tcl, Memory BIST, IEEE1687, Fishtail, IEEE1500, DFT RTL generation, IEEE1149.1, ATPG SAF, Spyglass DFT, VHDL, MBIST verification, ATPG, TDF, Spyglass LINT

DFT verification, IEEE1149, CTL generation, MBIST, Scan, ASIC SoC designs, DFT validation, 1500, 1687, DFT EDA tools, Dft, timing generating test cases, Analog IPs, HSIOs, debugging GLS

boundary scan , Technical Leadership, Perl, Python, Tcl, test compression, scan compression, DFT signoff, test access strategies, pattern optimization, DFT methodologies, MBIST, DFT architecture definition, Failure Analysis, ATPG, silicon bring-up, yield ramp, LBIST

Perl, Python, Dft, SV, coverage metrics, Profiling Tools, Uvm, X prop, constrained random testing

boundary scan , Vcs, Perl, Python, Tcl, Scan Insertion, Post-silicon validation, P1687, TetraMax, Gate level simulation debugging, ATE patterns, JTAG protocols, ATPG, Tessent tool sets, TestMax

Python, Perl, Dft, Uvm, SV, Profiling Tools, constrained random testing, coverage metrics